1. Field of the Invention
The present invention relates to a duty cycle correction circuit of a delay locked loop (DLL) and the delay locked loop having the duty cycle correction circuit, and more particularly, to a duty cycle correction circuit and a delay locked loop having the same, capable of controlling a duty rate of the duty cycles.
2. Description of the Related Art
Generally, a delay locked loop (DLL) receives external clock signals from outside a system and generates internal clock signals synchronized to the external clock signals. Here, the system includes devices such as logic devices or semiconductor devices using external clock signals.
For example, the DLL is applicable to a cash memory device for increasing a data transmission rate between a DRAM and a CPU of a computer, or a synchronous DRAMO, RAMBUSR DRAM, etc., as well as various type logic devices.
A double date rate (DDR) technique has been developed in order to improve bandwidths of memory systems. The memory systems uses rising edges and falling edges of internal clock signals. In that case, a duty cycle of the internal clock signal is an important factor for maintaining a timing margin maximally in a high performance memory system.
That is, in a case where the duty cycle of the internal clock signal is not exactly 50%, errors generated by an offset deviation from 50% reduce the timing margin of the high performance memory system. For this reason, a device for compensating distortion of the duty cycle due to changes in processes, voltages, and temperatures is necessary. That is, a duty cycle correction circuit used in the DLL is a circuit for correcting a duty cycle of an internal clock signal.
FIG. 1 is a block diagram of a conventional delay locked loop. Referring to FIG. 1, a DLL 100 comprises a DLL core 110, a clock buffer 130, and a duty cycle correction circuit 150.
The DLL core 110 as an important component of the DLL receives an external clock signal ECLK, and generates an internal clock signal ICLK synchronized to the external clock signal ECLK.
The clock buffer 130 includes a plurality of inverters 131, 133, 135, . . . , 137 connected serially to each other, buffers the internal clock signal ICLK, and generates a reference clock signal CLK and a complementary reference clock signal CLKB.
The inverter 131, as known well in the related field, consists of a PMOS transistor P1 and a NMOS transistor N1 that are serially connected between a source voltage VDD and a ground voltage VSS. The remaining inverters 133, 135, . . . , 137 have the same construction as the inverter 131. A method for generating the reference clock signal CLK and the complementary reference clock signal CLKB is obvious to one of ordinary skill in the art.
In the case where the PMOS transistor P1 and the NMOS transistor N1 of the respective inverters 131, 133, 135, . . . , 137 are the same in a ratio of channel width to channel length, the clock buffer 130 can output differential clock signals (CLK/CLKB) each having a duty cycle of 50%.
However, in the case where the duty cycle of the differential reference clock signals CLK/CLKB is not exactly 50% but 45% or 55% (referred to as “in the case where a duty error is generated”) due to changes of processes, voltages, and temperatures, the timing margin of the high performance memory system is reduced.
To solve this problem, the duty cycle correction circuit 150 converts the differential reference clock signals CLK/CLKB into duty offset information DCC/DCCB, and feeds back the duty offset information DCC/DCCB to the DLL core 110. Accordingly, the DLL core 110 controls the duty cycle of the internal clock signal ICLK to be exactly 50%, in response to the duty offset information DCC/DCCB.
However, since the duty cycle correction circuit 150 is always operated while the DLL 100 is being operated, it is not recognized whether the differential reference clock signals CLK/CLKB with the 50% duty cycle are generated by interoperation of the clock buffer 130 and the duty cycle correction circuit 150, or by a main operation of the clock buffer 130.
That is, in the case where a duty error is generated, it is difficult to correctly analyze whether the duty error is generated by the clock buffer 130 or by the duty cycle correction circuit 150.